Reviewing 4-to-2 Adders for Multi-Operand Addition

Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be superior to other types. This paper analyses the use of various 3and 4-element redundant digit sets for radix 2, and compare their adder implementations using various encodings of the digits and carries. It is shown that theoretically they are equivalent, and differences in their implementations need only be very marginal. Another recent proposal for the use of the digit-set f0; 1; 2; 3g, with a special 3-bit encoding of digits, is analyzed and some optimizations are shown, including the possibility of using a 2-bit encoding, simplifying the wiring of a multiplier tree. All these proposed designs are shown to be equivalent to a standard 4-to-2, carry-save adder, except possibly for a few signal inversions. 1. Introdu tion When implementing fast multipliers in VLSI, a major part of area and time is spent on accumulating partial products using some kind of tree structures. Originally these were based on the use of full-adders (and occasionally at the ends some half-adders), reducing the sum of three rows to the sum of two rows, using either the Wallace[17] or Daddaorganizations [2] of the tree structure. As these structures are not very regular to lay out due to the 3-to-2 structure, it was suggested to use 4-to-2 adders which allow the use of binary tree structures. [18] seems to be the first to propose their use, based on the carry-save representation, where two addends are considered an encoding of a single operand represented using the redundant digit-set f0; 1; 2g. Thus the 4-to-2 adder can be considered an adder taking two such operands and adding them to produce the result in the same representation. This addition can be performed in digit parallel, and thus in constant time, using an array of such digit adders. Radix 2 signed-digits for 4-to-2 adders over the digit-set f 1; 0; 1g were then later proposed in [15, 5]. Recently [3] proposed using the digit-set f0; 1; 2; 3g with a special 3-bit encoding of the digits, and most recently [10] compared various 3and 4-element digit sets using some particular encodings, claiming significant differences in the implementation of these. Other publications discussing multiplier organizations are [16, 11, 6, 7, 8, 9, 12, 19], and plenty more. After an introduction in Section 2 on the standard carry-save 4-to-2 adder, and some results on the use of signals with negative weights, Section 3 goes through a detailed review of a series of 4-to2 adders recently presented in [10]. These are all based on digit codings of the form d = 2dh dl for redundant digit-sets with 3 or 4 elements, and using a special technique denoted equal-weight grouping, or EWG. Here columns of bits of the same weight are accumulated, but producing a This work has been supported by the the Danish Natural Science Foundation, grant no. 9801811 sum represented in the various digit-sets. Results from SPICE simulations on the designs were presented, whereupon the authors then postulate some claims on the relative performances when using the investigated digit-sets. The following Section 4 then shows that all these designs can be implemented using the very same basic 4-to-2 carry-save adder, just using alternative external connections and possibly a few inverters. Hence there are no principal differences between the use of the various digit sets, as opposed to the claims of the paper, nor to the use of the digit encodings proposed or the 4-element digit-sets. Section 5 reviews some other recent results from [3], where the use of the digit-set f0; 1; 2; 3g and a special 3-bit encoding of that digit-set is employed. The authors claim to achieve fairly significant speed-ups by this encoding. By a detailed analysis and identification of some basic building blocks, it is shown that it is not necessary to use the particular 3-bit encoding to obtain the same effect, there is an equivalent 2-bit encoding. It is found that a saving in the wiring can be obtained by reorganizing the building blocks. Finally it is then shown that this design is also equivalent to one based on the standard 4-to-2 carry-save adder. In Section 6 conclusions are drawn. 2. A basi building blo k. We will start by looking at the basic functionality of a 4-to-2 adder, whose purpose in a multiplier (and other multi-operand addition problems) is reducing the sum of four binary operands to the sum of two. The operands can be partial products as generated and delivered in parallel at the leaves of the tree, or at the internal nodes of the tree they can be the result delivered as pairs of operands, forming the result of other 4-to-2 adders. In general we shall assume that such operands and results can have a specific positive or negative weight (is to be added or subtracted). A pair of two bits of positive weight can be interpreted as a digit in the set f0; 1; 2g, the carrysave digit-set, employing the carry-save encoding: 0 00 1 01 or 10 2 11 (1) where it may be noted that the digit value 1 has two encodings. Usually the 4-to-2 adder is considered an adder taking two such carry-save operands, and delivering the sum of these in the same carry-save representation. But alternatively interpreted at the digit level, it may also be considered a digit-set converter from the set f0; 1; 2g+f0; 1; 2g = f0; 1; 2; 3; 4g into the set f0; 1; 2g, where such a conversion can be pictured in a diagram [4]: f0; 1; 2; 3; 4g ? f0; 1; 2g ? f0; 1; 2; 3g f0; 1g f0; 1g ? f0; 1g ? f0; 1; 2g f0; 1g f0; 1g The converter or 4-to-2 adder can be realized by a combination of two full adders as in Figure 1, where the tuple (i1; i2), respectively (i3; i4), is the carry-save encoding of the operands, and (o1; o2) represents the result. Note that carries ( 0in; 00 in) similarly is a carry-save encoding of the incoming “double” carry, and ( 0out; 00 out) of the outgoing carry, corresponding to the previous conversion diagram. FA i1 i2 i3 i4 6 0out FA 0in -o1 6 00 out 00 in-o2 Carry-Save 4-to-2 Adder 6 0out 0in 00 in 6 00 out -o1 -o2 i4 i3 i2 i1 111 11 1 1 2 2 Figure 1. 4-to-2 carry-save adder composed of two full adders, and “box” version. A particularly efficient realization of a 4-to-2 adder was shown in [7], as illustrated in Figure 2, where the XOR-gates were implemented by MUXes using pass-transistors. mux 10 i4 i3 mux 10 mux 10 0in -o1 00 in -o2 mux 10 6 00 out mux 10 i2 mux 10 i1 6 0out Figure 2. 4-to-2 carry-save adder built of multiplexers. Note that the addition of the carry 00 in is obtained at no cost in Figures 1 and 2, corresponding to the second conversion in the conversion diagram above being without cost in logic. The transistor implementation of the XOR-gates in [7] uses a “dual-rail” representation of signals, these being provided and used in true as well as in inverted form. This implies that inversion of a signal can be realized by twisting wires, and thus at no cost in logic. For the following discussion we will use the simplified “box”-version of Figure 1, not being concerned with the actual implementation of the logic. Signals are marked with their relative weight. In Figures 1 and 2, and according to the carry-save representation, the signals i1; i2; i3; i4; 0in; 00 in; o1 and o2 all have the weight 1, while 0out and 00 out have weight 2, corresponding to the equation 2( 0out + 00 out) + (o1 + o2) = i1 + i2 + i3 + i4 + 0in + 00 in: (2) We will in the following assume that o2 = 00 in, since this allows 00 in to be added in at no cost. Thus we have the following defining equations o1 = (i1 + i2 + i3 + i4 + 0in) mod 2 o2 = 00 in 0out + 00 out = (i1 + i2 + i3 + i4 + 0in) div 2; (3) where the pair 0out; 00 out provides a carry-save encoding of the combined carry in f0; 1; 2g. To allow changes in the weights for other digit sets, following [1] we note this theorem: Theorem 1 Let a binary signal b 2 f0; 1g have associated weight w, so that the value of the signal is v = w b. Inverting the signal into 1 b, while at the same time negating the sign of the weight, changes its value into v0 = v w, i.e., the value is being biased by the amount w. Proof: Trivial since v0 = ( w)(1 b) = wb w = v w. 2 When changing the interpretation of input signals as representation of values, it is then necessary to perform equivalent changes in the interpretation of the output signals. E.g., when the the domain of input to an adder or a digit-set conversion is being biased, the output must be equivalently biased. Now consider the base 2 digit-set f 1; 0; 1g using the signed-digit encoding (also denoted borrow-save), where two bit strings are considered a string of digits: Neg. weight .. . . . . . . . . . . . . . . . ................ . Pos. weight obtained by pairing bits using the digit encoding: 1 10 0 00 or 11 1 01; (4) where the left-most bit has negative weight. The conversion diagram for the addition of two signeddigit operands then may look as: f 2; 1; 0; 1; 2g ? f0; 1; 2g ? f 1; 0; 1; 2g f 1; 0g f 1; 0g ? f 1; 0g ? f 1; 0; 1g f0; 1g f0; 1g If in Figure 1 we change the input so that (i1; i2) and (i3; i4) represent signed-digits, with i1 and i3 respectively having negative weight and the signals thus delivered inverted, then the input is being biased by 2. The output must then according to equation (2) be equivalently biased, which is possible by changing the sign of 0out by inverting its signal value. But then 0in must also change sign, which changes the bias in the input to 3. Finally, to compensate we must change the sign of the weight of o1, corresponding to the output (o1; o2) now representing a signed-digit, hence the signals must now satisfy the following equations: 2((1 0out) + 00 out) + ((1 o1) + o2) = (1 i1) + i2 + (1 i3) + i4 + (1 0in) + 00 in or 2( 0out + 00 out) + ( o1 + o2) = i1 + i2 i3 + i4 0in + 00 in and the equivalent equations derived from (3). Inverting the signals appropriately in Figure 1 we obtain Figure 3. Carry-Save 4-to-2 Adder 6 0out 0in 00 in 6 00 out -o1 -o2 i4 i3 i2 i1 111 11 1 1 2 2 Figure 3. 4-to-2 signed-digit adder obtained from a carry-save adder Theorem 2 In a computational model where inversion is without cost in area and time, radix 2 signed-digit addition can be realized at exactly the same cost as carry-save addition. Observe that if an array of such adders are connected (here vertically) to form an n-digit adder, then no inversions are needed between the individual adders. Similarly if a tree of such arrays are formed to perform multi-operand addition (here horizontal connections), then all the inversions internally in the tree can be eliminated. Theorem 3 Multi-operand addition of radix 2 signed-digit operands can be implemented by a tree of carry-save adders, by inverting all negatively weighted signals on input as well as on output, but with no changes internally to the tree. 3. Codings of the form 2dh dl. Recently in [10] various radix 2 redundant digit-sets, using encodings of the form (dh; dl) with d = 2dh dl, were suggested and analyzed, employing a particular way of implementation denoted equal-weight grouping or EWG, to be described below. The digit-sets investigated were D(SD) = f 1; 0; 1g D(CS2) = f0; 1; 2g D(SD3( )) = f 2; 1; 0; 1g D(CS3) = f0; 1; 2; 3g D(SD3(+)) = f 1; 0; 1; 2g: (5) The digit-sets D(SD) and D(SD3( )) are coded as d = 2dh + dl, corresponding to a 2’s complement encoding of the digit d. Since the digit-set D(SD) does not include 2, the bit-pattern (dh; dl) = (1; 0) is not valid in the SD representation. The set D(SD3(+)) is realized by changing the sign of both components, i.e., d = 2dh dl. The D(CS3) and D(CS2) digit-sets are coded with d = 2dh + dl, where the bit-pattern (dh; dl) = (1; 1) is invalid in the D(CS2) representations. Since the encodings employ weights differing by a factor of 2, neighboring digits di and di 1 in a radix representation overlap one another, i.e., dli has the same weight as dhi 1, ..... . . . . . . . . . . . . . . . ............ ..... . . . . . . . . . . . . . . . . ............ but accumulation of several bit-vectors from the encoding of digit vectors can still be performed in vertical columns. This is what the authors of [10] denote equal-weight grouping or EWG-form. Normally redundant adders are used to reduce the sum of two digit-vectors to a single redundant digit-vector, absorbing and emitting suitable carries. With additions of the form D+D ! D, where D is one of the above listed CS digit-sets, e.g., withD = D(CS3), thenD+D = f0; 1; 2; 3; 4; 5; 6g. With EWG, bits from the encoding of two neighboring positions are added, the summation takes bits in a column forming a sum in f0; 1; 2; 3; 4g, but producing the resulting digit inD(CS3) = f0; 1; 2; 3g as shown in the following diagram (without the carries): .. . . . . . . . . . . . . . . . . .............. .. ..... . . . . . . . . . . . . . . . . ............ ..... . . . . . . . . . . . .